library ieee;
use ieee.std_logic_1164.all;

package mis_componentes is

component sum4bits is
port(a:in std_logic_vector(3 downto 0);
	 b:in std_logic_vector(3 downto 0);
	 s:out std_logic_vector(3 downto 0);
	 Cout:out std_logic);
end component;

component sum1bit is
	port(a,b,Cin:in std_logic;
		s,Cout:out std_logic);
end component;

component complemento2 is
port(a,b,c,d:in std_logic;
	f:out std_logic_vector(3 downto 0);
	Cout:out std_logic);
end component;

end mis_componentes;